Embedded SiGe stressor with tensile strain for NMOS current enhancement
US7612389B2 · kind B2 · utility
7Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Oct 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
MOS devices having localized stressors are provided. Embodiments of the invention comprise a gate electrode formed over a substrate and source/drain regions formed on either side of the gate electrode. The source/drain regions include an embedded stressor and a capping layer on the embedded stressor. Preferably, the embedded stressor has a lattice spacing greater than the substrate lattice spacing. In a preferred embodiment, the substrate is silicon and the embedded stressor is silicon germanium. A method of manufacturing is also provided, wherein strained PMOS and NMOS transistors may be formed simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.