Sequence independent non-overlapping digital signal generator with programmable delay
US7612595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2007 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Dec 6, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating non-overlapping clock signals includes a programmable delayed reference clock signals circuit to produce a plurality of delayed reference clock signals and a plurality of delay clock signal generators, operatively connected to the programmable delayed reference clock signals circuit, to generate non-overlapping clock signals. Each delay clock signal generator includes a latch or flip-flop to control a delay in a rising edge of a clock signal and to output a first signal, another latch or flip-flop to control a delay in a falling edge of a delayed clock signal and to output a first signal, and a logic circuit to generate the clock signal from the first and second signals. The latches or flip-flops independently control a delay in the rising edge of the clock signal in response to one of the plurality of delayed reference clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.