Processing multiplex sublayer data unit data in hardware
US7613186B2 · kind B2 · utility
0Cited by
9References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 2004 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Sep 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention concerns an apparatus comprising a data unit, a memory and a control unit. The data unit may be configured to generate an output signal comprising a series of frames each having a header and a payload in response to an input signal comprising a series of words. The memory may be configured to hold the output signal and to interface with a device. The control unit may be configured to present one or more control signals configured to control the data unit and the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.