System and method utilizing programmable ordering relation for direct memory access
US7613850B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2008 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Dec 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.