Device and method for enabling efficient and flexible reconfigurable computing
US7613902B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2005 |
| Grant date | Nov 3, 2009 |
| Priority date | — |
| Expiry date | Sep 23, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-efficient, distributed reconfigurable computing system and method are provided. A reconfigurable computing system may include an embedded controller for performing real-time control and initialization and circuitry that supports data-flow driven execution of processing phases. The circuitry may include processing elements such as RAM-based field programmable gate array devices and direct memory access engines. The processing elements can be configured for one or more functions or operations of a program and then reconfigured for other functions or operations of the program. The processing elements can be configured or reconfigured to construct a desired sequence of operations in real-time. A processing element may be divided into slots, each of which includes a substantially similar amount of resources. A processing element includes one or more wrappers, and a wrapper may occupy a slot or a group of slots. Layered software architecture separates control software from implementation software. The control software that contains the knowledge of the overall algorithm is implemented in higher-order language such as C++. This software typically runs on a general-purpose computer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.