Clock generation method and device for decoding from an asynchronous data signal
US7614564B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | May 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.