Semiconductor device and control method in semiconductor device
US7614565B2 · kind B2 · utility
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1References
5Claims
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Key dates
| Filing date | Nov 28, 2005 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load detection circuit 40 detects a load value of a load portion 100 via a terminal DQ. A reference load, corresponding to the load of a probe, is output from a reference load output section. A comparison circuit 60 judges whether the detected load value matches the reference load, and outputs a control signal if matched. If this control signal is input, an input and output buffer 30 stops the output of the data from a memory cell 10 to the terminal DQ, or outputs a specific logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.