Charge trap flash memory device, fabrication method thereof, and write/read operation control method thereof
US7615446B2 · kind B2 · utility
20Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | May 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/687
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
In one aspect, a charge trap flash memory device is provided which includes a semiconductor substrate, source and drain regions which are spaced apart in an active region of the semiconductor substrate to define a channel region therebetween, a tunneling dielectric layer located on the channel region, an organic polymer thin film located on the tunneling dielectric layer, metal or metal oxide nano-crystals embedded in the organic polymer thin film, and a gate located on the organic polymer thin film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.