Semiconductor wafer and semiconductor device, and method for manufacturing same
US7615781B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Dec 5, 2006 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Jun 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is a room for improvement in conventional semiconductor devices in terms of reducing the chip area. A semiconductor device 1 comprises an evaluation transistor 10 (first characteristic evaluation device), an evaluation transistor (second characteristic evaluation device), measurement pads 30 (first measurement pads) and measurement pads 40 (second measurement pads). The measurement pad 30 and the measurement pad 40 are provided in different layers in the interconnect layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.