Charge trap memory with avalanche generation inducing layer
US7615821B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Jan 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.