Data retention in operational and sleep modes
US7616041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a tristateable device, said tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that sa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.