High-speed mixed analog/digital PRML data detection and clock recovery apparatus and method for data storage
US7616547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2005 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Aug 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.