Mechanism and method for simultaneous processing and debugging of multiple programming languages
US7617084B1 · kind B1 · utility
9Cited by
14References
38Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method, mechanism, and computer usable medium for simultaneous processing or debugging of multiple programming languages. A particularly disclosed approach provides a method and mechanism for resolving the issue of simultaneous debugging of hardware represented by an HDL, e.g., Verilog or VHDL, and software, e.g., represented by C, C++, SystemC code. This approach overcomes the problem of the HDL portion of the design being inaccessible when C, C++ or SystemC code is debugged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.