Electrostatic discharge device verification in an integrated circuit
US7617467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2006 |
| Grant date | Nov 10, 2009 |
| Priority date | — |
| Expiry date | Oct 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.