Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process
US7618837B2 · kind B2 · utility
10Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Oct 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/40
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The invention discloses a novel flexible, modular fabrication method for integrated high aspect ratio single crystal silicon microstructures designed and manufactured in a post conventional CMOS process (Post-CMOS). The method involves the standard circuits formation, the electrical isolation trenched etching and refilling, backside etching, interconnection formation, and structure releasing. Further, a method of tailoring the trench profile for refill the trench fully without void is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.