Semiconductor package and method for manufacturing the same
US7619316B2 · kind B2 · utility
2Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2007 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Oct 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10253
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.