Asynchronous phase acquisition unit with dithering
US7619483B2 · kind B2 · utility
3Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2007 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop includes a phase acquisition unit receiving a sampled input signal and applying its output to a first input of a digital phase detector, a digital controlled oscillator producing a digital output, and a feedback path coupling the digital output of the digital controlled oscillator to a second input of the digital phase detector in the digital domain. The input signal may be sampled asynchronously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.