Methods and systems for reducing a sign-bit pulse at a voltage output of a sigma-delta digital-to-analog converter
US7619549B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 18, 2007 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | May 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
For a sigma-delta digital-to-analog converter (SD DAC) that includes a voltage output and a low-pass filter having a given order, methods and systems for reducing a sign-bit pulse at the voltage output of the SD DAC without requiring use of a higher order low-pass filter are disclosed. A method includes receiving a first waveform and a second waveform, the first and second waveforms having a first phase relationship; setting the first phase relationship between the first and second waveforms to a second phase relationship by aligning at least one of the first and second waveforms such that a transition of the second waveform is approximately half way between a rising edge and adjacent falling edge of the first waveform; upon setting the second phase relationship, multiplying the first and second waveforms to produce a digital input; and providing the digital input to the SD DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.