Thin film transistor array panel and manufacturing method thereof
US7619694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1393
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor array panel according to an embodiment includes: a substrate; a plurality of gate line formed on the substrate; a plurality of first capacitor electrodes formed on the substrate and separated from the gate lines; a plurality of data line intersecting the gate lines; a plurality of thin film transistor connected to the gate lines and the data lines; a plurality of second capacitor electrodes disposed on the first electrode; a plurality of interconnections connected to the second capacitor electrodes and the thin film transistor and disposed symmetrical to the data lines; and a plurality of pixel electrode, each pixel electrode including a first subpixel electrode connected to one of the thin film transistors and a second subpixel electrode connected to one of the first capacitor electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.