Method and apparatus for detecting frequency lock in a system including a frequency synthesizer
US7620126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | May 3, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency synthesizer lock detection system is disclosed that distributes a frequency synthesizer output signal across a distribution network to one or more receptor circuits. The distribution network may exhibit delay and other distortion that may cause the downstream signal arriving at the receptor circuit to lose frequency lock with both the frequency synthesizer output signal and a reference clock signal that controls the frequency of the synthesizer output signal. The lock detection system tests the downstream signal to determine if the downstream signal exhibits a lock with respect to the reference clock that determines the operating frequency of the frequency synthesizer. In this manner, lock of the downstream signal to the reference clock signal may be accurately assessed in one embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.