Method and system for reducing the time-to-market concerns for embedded system design
US7620678B1 · kind B1 · utility
11Cited by
71References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 12, 2003 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Nov 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects for reducing the time-to-market concerns for embedded system design are described. The aspects include providing an infrastructure to support a plurality of heterogeneous processing nodes as a reconfigurable network. Further included is utilizing the infrastructure to customize at least one of the heterogeneous processing nodes according to individualized design needs to achieve a desired embedded system signal processing engine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.