Functional DMA performing operation on DMA data and writing result of operation
US7620746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Apr 30, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.