Mapping memory in a parallel processing environment
US7620791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2006 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Oct 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0844
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further includes a plurality of memory interface modules including circuitry to access a respective external memory, each memory interface module coupled to a switch of at least one tile. At least some of the tiles are configured to access an address in an external memory by sending from the switch a packet that includes a physical memory address that includes the external memory address and information identifying the corresponding external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.