Processing system, memory and methods for use therewith
US7620792B2 · kind B2 · utility
4Cited by
3References
43Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 21, 2006 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Feb 2, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory includes an array of memory cells arranged in a plurality of rows and a plurality of columns. An address transform module receives a logical address including a logical column address and logical row address, and transforms the logical address into a physical address having a physical row address and a physical column address. An address decoder module accesses an individual memory cell of the array of memory cells based on the physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.