Instructions for efficiently accessing unaligned vectors
US7620797B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Feb 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector from a naturally-aligned memory region encompassing the source address, and in doing so rotating the bytes of the vector to cause the byte at the specified source address to reside at the least-significant byte position within the vector for a little-endian memory transaction, or causing said byte to be positioned at the most-significant byte position within the vector for a big-endian memory transaction. In a variation on this embodiment, the processor is also configured to execute a store-swapped instruction directed to a destination address by storing a vector into a naturally-aligned memory region encompassing the destination address, and in doing so rotating the bytes of the vector to cause the least significant byte of the vector to be stored to at the specified destination address on a little-endian processor, or causing the most significant byte of the vector to be stored to the destination address said on a big-en…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.