Jitter tolerant delay-locked loop circuit
US7620839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2005 |
| Grant date | Nov 17, 2009 |
| Priority date | — |
| Expiry date | Apr 23, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.