Interconnection architecture and method of assessing interconnection architecture
US7622779B2 · kind B2 · utility
9Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2003 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Sep 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-celled chip. The chip includes a plurality of hexagonal cells arranged in an array. A plurality of interconnects including Y's connect the cells in clusters of three cells each, so that each of the cells is interconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.