Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme

US7622955B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Ramaprasath Vilangudipitchai · San Diego, US
• Sumanth Katte Gururajarao · Dallas, US
• Hugh Mair · Fairview, US
• Alice Wang · Allen, US
• Uming Ko · Plano, US
• Sushma Honnavara-Prasad · San Jose, US

Key dates

• Filing date: Apr 17, 2008
• Grant date: Nov 24, 2009
• Expiry date: May 28, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0375
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.