Dynamic voltage scaling for self-timed or racing paths
US7622979B2 · kind B2 · utility
9Cited by
2References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Jan 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.