Multi-loop phase locked loop circuit
US7622996B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Dec 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.