Method for dynamically tuning the clock frequency of an oscillator and corresponding oscillating system
US7622997B2 · kind B2 · utility
5Cited by
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17Claims
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Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Aug 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0991
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.