Digital calibration loop for an analog to digital converter
US7623050B2 · kind B2 · utility
8Cited by
18References
32Claims
0Family size
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Key dates
| Filing date | Dec 13, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Dec 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/363
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to counter effects of an offset voltage by calibrating an analog-to-digital converter (ADC). A digital calibration loop minimizes the effects of offset voltage to improve ADC accuracy as well as provide a low-power, submicron-scale ADC. A calibration circuit senses an ADC output and adjusts a variable calibration voltage to counter the effects of the offset voltage. Reduction of the offset voltage effects increases the ADC accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.