Read-only memory device and related method of design
US7623367B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.