Nonvolatile semiconductor memory device
US7623380B2 · kind B2 · utility
4Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2006 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Oct 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.