Accessing semiconductor memory device according to an address and additional access information
US7623406B2 · kind B2 · utility
2Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Feb 15, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a decoder, and an access control unit. The decoder generates a word line voltage according to an address for a plurality of memory cells in the memory cell array. The access control unit controls access to the plurality of memory cells according to the word line voltage and additional access information separate from the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.