High speed receive equalizer architecture
US7623600B2 · kind B2 · utility
10Cited by
4References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Sep 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03617
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.