Ethernet controller with excess on-board flash for microcontroller interface
US7624157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Dec 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/901
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller. A memory interface allows the processing system to interface with the second portion of the memory, such that the processing system has an expanded memory capability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.