Instructions for efficiently accessing unaligned partial vectors
US7624251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2007 |
| Grant date | Nov 24, 2009 |
| Priority date | — |
| Expiry date | Feb 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the load-swapped-partial instruction specifies a source address in a memory, which is possibly an unaligned address. Furthermore, an execution unit within the processor is configured to execute the load-swapped-partial instruction. This involves loading a partial-vector-sized datum from a naturally-aligned memory region encompassing the source address. While loading the partial-vector-sized datum, bytes of the partial-vector-sized datum are rotated to cause the byte at the specified source address to reside at the least-significant byte position within the partial-vector-sized datum for a little-endian memory transaction, or to cause the byte to be positioned at the most-significant byte position within the partial-vector-sized datum for a big-endian memory transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.