Via configurable architecture for customization of analog circuitry in a semiconductor device
US7626272B2 · kind B2 · utility
4Cited by
25References
22Claims
0Family size
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Key dates
| Filing date | Oct 7, 2008 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Oct 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.