Method of operating memory cell providing internal power switching
US7626853B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Apr 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations are provided that may be used to improve the writeability of individual memory cells providing internal power switching. For example, in one implementation, a method is provided for operating a memory device including a first static random access memory (SRAM) cell including first and second cross-coupled logic gates. The method includes providing a first power level to the first and second cross-coupled logic gates during a read operation performed on the first SRAM cell, and receiving a logic signal at the first SRAM cell. The method also includes switching within the first SRAM cell from providing the first power level to the cross-coupled logic gates to providing a second power level to the cross-coupled logic gates in response to the logic signal to facilitate writing a first logic state into the first SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.