2-write 3-read SRAM design using a 12-T storage cell
US7626854B1 · kind B1 · utility
6Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Feb 27, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.