Active bit line charge keeper
US7626878B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2007 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Aug 14, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth an active bit line charge keeper circuit for improving the reliability of a static random access memory (SRAM) circuit. The active bit line charge keeper circuit includes two sub-circuits, each disposed between bit line pairs within the SRAM circuit. The first sub-circuit mitigates residual state associated with over-developed read state on the bit lines. The second sub-circuit mitigates the effects of residual state associated with reading one value on a given pair of bit lines and subsequently writing a different value. By mitigating the effects of residual state within an SRAM circuit, higher reliability at a given performance level may be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.