Digital pulse width modulator
US7627032B2 · kind B2 · utility
2Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Dec 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.