Clock-edge modulated serial link with DC-balance control
US7627044B2 · kind B2 · utility
11Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2005 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jun 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.