Timing synchronization module and method for synchronously playing a media signal
US7627071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Dec 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4305
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit receives a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, while the reception-end clock signal has N clocks as generated. When the difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the synchronization processing unit controls media signal playing according to the reception-end clock signal and the procedure clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.