Long-integer multiplier
US7627625B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 22, 2004 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jun 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder circuit for multiplying two long integers deploys a network of adders for summing a succession of words of the long integers to generate intermediate results. The number of addends varies as a function of bit position and the network of adders is designed to reduce the number of levels of adders in the network according to a maximum number of expected addends. A number of strategically placed extra adders may be positioned in the network to further reduce the number of levels. An output stage may be provided that adds sum and carry outputs of the network and retains a most significant bit for use with a subsequent calculation output of the network. The network may be configured so that a subsequent calculation by the network can commence before the previous calculation has been completed, the output of the previous calculation being fed back to the network at an intermediate level and its lowest (output) level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.