Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications
US7627802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Jul 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)}i). Each block ({right arrow over (b)}i) is of size (M) and is related to a unit vector ({right arrow over (e)}i). A summation operation on the blocks ({right arrow over (b)}i) given by CRC({right arrow over (b)})=Σbi·CRC({right arrow over (e)}i) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)}i)) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.