Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
US7627806B1 · kind B1 · utility
5Cited by
10References
23Claims
0Family size
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Key dates
| Filing date | May 17, 2006 |
| Grant date | Dec 1, 2009 |
| Priority date | — |
| Expiry date | Mar 26, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.