Bottom gate thin film transistor and method of manufacturing the same
US7629207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Jun 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/0229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.