Method of manufacturing a capacitor and method of manufacturing a semiconductor device using the same
US7629218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2006 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Dec 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
Example embodiments relate to a method of manufacturing a capacitor and a method of manufacturing a semiconductor device using the same. Other example embodiments relate to a method of manufacturing a capacitor having improved characteristics and a method of manufacturing a semiconductor device using the same. In a method of manufacturing a capacitor having improved characteristics, an insulation layer, including a pad therein, may be formed on a substrate. An etch stop layer may be formed on the insulation layer. A mold layer may be formed on the etch stop layer. The mold layer may be partially etched by a first etching process to form a first contact hole exposing the etch stop layer. The mold layer may be partially etched by a second etching process to form a second contact hole. The exposed etch stop layer may be etched by a third etching process to form a third contact hole exposing the pad. A native oxide layer on the exposed pad may be removed by a fourth etching process to form a capacitor contact hole. A conductive layer may be formed in the capacitor contact hole to form a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.